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3 Volt Intel StrataFlash(R) Memory
28F128J3, 28F640J3, 28F320J3 (x8/x16)
Datasheet
Product Features
Performance -- 110/115/120/150 ns Initial Access Speed -- 25 ns Asynchronous Page-Mode Reads -- 32-Byte Write Buffer --6.8 s per Byte Effective Programming Time Software -- Program and Erase suspend support -- Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Security -- 128-bit Protection Register --64-bit Unique Device Identifier --64-bit User Programmable OTP Cells -- Absolute Protection with VPEN = GND -- Individual Block Locking -- Block Erase/Program Lockout during Power Transitions
Architecture -- Multi-Level Cell Technology: High Density at Low Cost -- High-Density Symmetrical 128-Kbyte Blocks --128 Mbit (128 Blocks) --64 Mbit (64 Blocks) --32 Mbit (32 Blocks) Quality and Reliability -- Operating Temperature: -40 C to +85 C -- 100K Minimum Erase Cycles per Block -- 0.18 m ETOXTM VII Process (J3C) -- 0.25 m ETOXTM VI Process (J3A) Packaging and Voltage -- 56-Lead TSOP Package -- 64-Ball Intel(R) Easy BGA Package -- 48-Ball Intel(R) VF BGA Package (32 and 64 Mbit) (x16 only) -- VCC = 2.7 V - 3.6 V -- VCCQ = 2.7 V - 3.6 V
Capitalizing on Intel's 0.25 and 0.18 micron, two-bit-per-cell technology, the 3 Volt Intel StrataFlash(R) Memory (J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-per-cell storage technology to the flash market segment. Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFileTM memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash(R) memory (28F640J5 and 28F320J5) devices. J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash(R) memory devices. Manufactured on Intel(R) 0.18 micron ETOXTM VII (J3C) and 0.25 micron ETOXTM VI (J3A) process technology, the J3 memory device provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290667-013 February 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Intel StrataFlash(R) Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2003, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7 1.1 1.2 1.3 2.0 2.1 2.2 2.3 2.4 2.5 3.0 3.1 Document Purpose ...............................................................................................................7 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 Product Overview .................................................................................................................8 Ballout Diagrams ..................................................................................................................9 Signal Descriptions .............................................................................................................12 Block Diagram ....................................................................................................................13 Memory Map .......................................................................................................................14 Bus Operations ...................................................................................................................15 3.1.1 Read Mode ............................................................................................................16 3.1.2 Write ......................................................................................................................16 3.1.3 Output Disable .......................................................................................................16 3.1.4 Standby..................................................................................................................17 3.1.5 Reset/Power-Down ................................................................................................17 Device Commands .............................................................................................................17 Read Array..........................................................................................................................19 4.1.1 Asynchronous Page-Mode Read ...........................................................................19 Read Identifier Codes .........................................................................................................19 Read Status Register..........................................................................................................20 Read Query/CFI..................................................................................................................22 Byte/Word Program ............................................................................................................22 Write to Buffer .....................................................................................................................22 Program Suspend ...............................................................................................................23 Program Resume................................................................................................................24 Block Erase.........................................................................................................................24 Block Erase Suspend .........................................................................................................24 Erase Resume ....................................................................................................................25 Set Block Lock-Bit...............................................................................................................26 Clear Block Lock-Bits..........................................................................................................26 Protection Register Program ..............................................................................................27 7.3.1 Reading the Protection Register ............................................................................27 7.3.2 Programming the Protection Register....................................................................27 7.3.3 Locking the Protection Register .............................................................................27 Array Protection ..................................................................................................................30
Device Description ........................................................................................................................8
Device Operations .......................................................................................................................15
3.2 4.0 4.1 4.2 4.3 4.4 5.0 5.1 5.2 5.3 5.4 6.0 6.1 6.2 6.3 7.0 7.1 7.2 7.3
Read Operations ..........................................................................................................................19
Programming Operations ...........................................................................................................22
Erase Operations .........................................................................................................................24
Security Modes ............................................................................................................................26
7.4
Datasheet
3
Contents
8.0
Special Modes.............................................................................................................................. 30 8.1 8.2 Set Read Configuration ...................................................................................................... 30 8.1.1 Read Configuration................................................................................................ 30 STS..................................................................................................................................... 30 Power-Up/Down Characteristics......................................................................................... 32 Power Supply Decoupling................................................................................................... 32 Reset Characteristics.......................................................................................................... 32 Absolute Maximum Ratings ................................................................................................ 33 Operating Conditions .......................................................................................................... 34 DC Current Characteristics................................................................................................. 35 DC Voltage Characteristics................................................................................................. 36 Read Operations................................................................................................................. 37 Write Operations................................................................................................................. 39 Block Erase, Program, and Lock-Bit Configuration Performance....................................... 40 Reset Operation.................................................................................................................. 42 AC Test Conditions............................................................................................................. 42 Capacitance........................................................................................................................ 43
9.0
Power and Reset.......................................................................................................................... 32 9.1 9.2 9.3 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6
10.0 Electrical Specifications ............................................................................................................. 33
11.0 AC Characteristics ...................................................................................................................... 37
Appendix A Write State Machine (WSM) .............................................................................................44 Appendix B Common Flash Interface..................................................................................................45 Appendix C Flow Charts .......................................................................................................................52 Appendix D Mechanical Information ...................................................................................................61 Appendix E Design Considerations.....................................................................................................64 Appendix F Additional Information......................................................................................................66 Appendix G Ordering Information .......................................................................................................67
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Datasheet
Contents
Revision History
Date of Revision 07/07/99 08/03/99 09/07/99 Version -001 -002 -003 Original Version A0-A2 indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries 12/16/99 -004 Changed Min program time to 211 s Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 03/16/00 -005 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of 0.45 V; Removed VOH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion 06/26/00 -006 Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7; not 2-7 Updated Table 16 bit 2 definition from R to PSS 2/15/01 -007 Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics-Read-Only Operations (1,2) Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC Characteristics-Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 s, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
(1,2,3)
Description
04/13/01
-008
Revised Section 7.0, Ordering Information
Datasheet
5
Contents
Date of Revision
Version
Description Added Figure 4, 3 Volt Intel StrataFlash(R) Memory VF BGA Package (32 Mbit) Added Figure 5, 3 Volt Intel StrataFlash(R) Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
07/27/01
-009
Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for -40 C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to 2.2 V Removed Note #4, Section 6.4 and Section 6.6 Minor text edits Added notes under lead descriptions for VF BGA Package Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
10/31/01
-010
Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits Added nomenclature for J3C (0.18 m) devices. Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added "TE" package designator for J3C TSOP package.
03/21/02
-011
12/12/02 01/24/03
-012 -013
6
Datasheet
28F128J3, 28F640J3, 28F320J3
1.0
1.1
Introduction
Document Purpose
This document contains information pertaining to the 3 Volt Intel StrataFlash(R) Memory device, J3. The purpose of this document is to facilitate the use of this product and describe the features, operations, and specifications of this device.
1.2
Nomenclature
AMIN: AMAX: Block: Clear: CUI: MLC: OTP: PLR: PR: PRD Program: RCR: RFU: Set: SR: SRD VPEN: VPEN: WSM: XSR AMIN = A0 for x8 AMIN = A1 for x16 32 Mbit AMAX = A21 64 Mbit AMAX = A22 128 Mbit AMAX = A23 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero (0) Command User Interface Multi-Level Cell One Time Programmable Protection Lock Register Protection Register Protection Register Data To write data to the flash array Read Configuration Register Reserved for Future Use Indicates a logic one (1) Status Register Status Register Data Refers to a signal or package connection name Refers to timing or voltage levels Write State Machine eXtended Status Register
1.3
Conventions
0x: 0b: k (noun): M (noun): Nibble Byte: Word: Kword: Kb: KB: Mb: MB: Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. A[21:1], SR[4,1] and D[15:0]). 7
Datasheet
28F128J3, 28F640J3, 28F320J3
2.0
2.1
Device Description
Product Overview
The 3 Volt Intel StrataFlash(R) memory family contains high-density memories organized as 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two 128Kbyte erase blocks. Blocks are selectively and individually lockable in-system. A 128-bit protection register has multiple uses, including unique flash device identification. The device's optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second-- independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/
8
Datasheet
28F128J3, 28F640J3, 28F320J3
BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 3, "Chip Enable Truth Table" on page 16) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 4 on page 14. When the device is disabled (see Table 3 on page 16) and the RP# signal is at VCC, the standby mode is enabled. When the RP# signal is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the Status Register is cleared.
2.2
Ballout Diagrams
Intel StrataFlash(R) Memory is available in three package types. Easy BGA in a 64-ball configuration, along with 56-lead TSOP (Thin Small Outline Package), support all offered densities. A 48-ball VF BGA package supporting the 32 and 64 Mbit device is also supported. Figure 1, Figure 2, and Figure 3 show the pinouts.
Datasheet
9
28F128J3, 28F640J3, 28F320J3
Figure 1. 3 Volt Intel StrataFlash(R) Memory Easy BGA Ballout
1 A A1 B A2 C A3 D A4 E D8 F BYTE# D0 G A23 128M H CE2# RFU VCC VSS D13 VSS Easy BGA Top View- Ball side down D7 A24 256M A24 D7 256M VSS D13 VSS VCC RFU CE2# Easy BGA Bottom View- Ball side up A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23 128M H D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE# G D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8 F A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4 E A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3 D VSS A9 CEO# A14 RFU A19 CE1# CE1# A19 RFU A14 CEO# A9 VSS A2 C A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1 B 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A
NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC). 3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).
Figure 2. 3 Volt Intel StrataFlash(R) Memory 56-Lead TSOP (32/64/128 Mbit)
3 Volt Intel StrataFlash Memory 28F160S3 NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 28F320J5 NC CE1 A21 A20 A19 A18 A17 A16 VCC(4) A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 32/64/128M A22(1) CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 Volt Intel StrataFlash Memory 32/64/128M A24(3) WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23(2) CE2 28F320J5 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC(4) DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 28F160S3 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
3 Volt Intel StrataFlash(R) Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
Highlights pinout changes
NOTES: 1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC). 3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC). 4. VCC = 5 V 10% for the 28F640J5/28F320J5.
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Datasheet
28F128J3, 28F640J3, 28F320J3
Figure 3. 3 Volt Intel StrataFlash(R) Memory VF BGA Ballout(32 and 64 Mbit)
1 A A14 B A15 C A16 D A17 E VCCQ F VSS
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1 A
A12
A9
VPEN
VCC
A20
A8
A5
A5
A8
A20
VCC
VPEN
A9
A12
A14 B
A11
WE#
RP#
A19
A18
A6
A3
A3
A6
A18
A19
RP#
WE#
A11
A15 C
A13
A10
A22
A21
A7
A4
A2
A2
A4
A7
A21
A22
A10
A13
A16 D
D14
D5
D11
D2
D8
CE#
A1
A1
CE#
D8
D2
D11
D5
D14
A17 E
D15
D6
D12
D3
D9
D0
VSS
VSS
D0
D9
D3
D12
D6
D15
VCCQ F
D7
D13
D4
VCC
D10
D1
OE#
OE#
D1
D10
VCC
D4
D13
D7
VSS
VF BGA 6x8 Top View - Ball Side Down
VF BGA 6x8 Bottom View - Ball Side Up
NOTES: 1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded. 2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC). 3. STS not supported on this package. 4. x8 not supported on this package.
Datasheet
11
28F128J3, 28F640J3, 28F320J3
2.3
Signal Descriptions
Table 1 lists the active signals used and provides a description of each. Table 1.
Symbol A0
Signal Descriptions (Sheet 1 of 2)
Type INPUT Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A[21:0] 64-Mbit: A[22:0] 128-Mbit: A[23:0] LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during CUI writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs D[6:0] are also floated when the WSM is busy. Check SR7 to determine WSM status. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, query, or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CHIP ENABLES: Activates the device's control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 3 on page 16), power reduces to standby levels. INPUT All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device (see Table 3 on page 16). RESET/ POWER-DOWN: Resets internal automation and puts the device in powerdown mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. STATUS: Indicates the status of the internal state machine. When configured in level mode (default mode), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS signal, see the Configurations command. Tie STS to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on D[7:0], while D[15:8] float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN VPENLK, memory contents cannot be altered. DEVICE POWER SUPPLY: With VCC VLKO, all write attempts to the flash memory are inhibited.
A[23:1]
INPUT
D[7:0]
INPUT/ OUTPUT
D[15:8]
INPUT/ OUTPUT
CE0, CE1, CE2
RP#
INPUT
OE#
INPUT
WE#
INPUT
STS
OPEN DRAIN OUTPUT
BYTE#
INPUT
VPEN
INPUT
VCC
SUPPLY
12
Datasheet
28F128J3, 28F640J3, 28F320J3
Table 1.
Symbol VCCQ GND NC RFU
Signal Descriptions (Sheet 2 of 2)
Type POWER SUPPLY Name and Function I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC. GROUND: Do not float any ground signals. NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device functionality and enhancement.
2.4
Block Diagram
Figure 4. 3 Volt Intel StrataFlash(R) Memory Block Diagram
D[15:0]
VCCQ
Output Buffer
Input Buffer
Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register
I/O Logic Data Register CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Command User Interface
A[2:0]
Multiplexer Data Comparator
Y-Decoder A[MAX:MIN] Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch
STS VPEN
Address Latch Address Counter
X-Decoder
VCC GND
Datasheet
13
28F128J3, 28F640J3, 28F320J3
2.5
Memory Map
Figure 5. 3 Volt StrataFlash(R) Memory Map
A [MAX : MIN]
FFFFFF FE0000
A [MAX : MIN]
7FFFFF
128-Kbyte Block
127 7F0000
64-Kword Block
127
7FFFFF
3FFFFF
128-Kbyte Block
7E0000
63 3F0000
64-Kword Block
63
128-Kbyte Block
3E0000
31 1F0000
64-Kword Block
31
03FFFF
01FFFF
128-Kbyte Block
020000 01FFFF 000000
1 0 010000 00FFFF 000000
64-Kword Block 64-Kword Block
1 0
128-Kbyte Block
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
14
32 Mbit
Datasheet
64 Mbit
3FFFFF
1FFFFF
128 Mbit
28F128J3, 28F640J3, 28F320J3
3.0
Device Operations
This section provides an overview of device operations. The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. The system CPU provides control of all insystem read, write, and erase operations of the device via the system bus. Device commands are written to the CUI to control all of the flash memory device's operations. The CUI does not occupy an addressable memory location; it's the mechanism through which the flash device is controlled.
3.1
Bus Operations
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Table 2.
Mode Read Array Output Disable Standby
Bus Operations
RP# VIH VIH VIH VIL VIH VIH VIH VIH VIH CE0,1,2 Enabled Enabled Disabled X Enabled Enabled Enabled Enabled Enabled OE#(2) VIL VIH X X VIL VIL VIL VIL VIH WE#(2) VIH VIH X X VIH VIH VIH VIH VIL Address X X X X See Table 5 See Table 4.4 X X X VPEN X X X X X X X X VPENH Data(3) DOUT High Z High Z High Z Note 8 Note 9 DOUT D7 = DOUT D[15:8] = High Z D[6:0] = High Z DIN X 6,10,11 STS (default mode) High Z(7) X X High Z(7) High Z(7) High Z(7) Notes 4,5,6
Reset/Power-Down Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM on) Write
NOTES: 1. See Table 3 on page 16 for valid CE configurations. 2. OE# and WE# should never be enabled simultaneously. 3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high. 4. Refer to DC Characteristics. When VPEN VPENLK, memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address signals, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Section 4.2, "Read Identifier Codes" on page 19 for read identifier code data. 9. See Section 4.4, "Read Query/CFI" on page 22 for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC is within specification.
Datasheet
15
28F128J3, 28F640J3, 28F320J3
Table 3.
Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND.
3.1.1
Read Mode
To perform a bus read operation, CE# (Please refer to Table 3 on page 16) and OE# must be asserted. CE# is the device-select control; when active, it enables the flash memory device. OE# is the data-output control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See Section 11.1, "Read Operations" on page 37. Refer to Section 4.0, "Read Operations" on page 19 for details on reading from the flash array, and refer to Section 8.0, "Special Modes" on page 30 for details regarding all other available read states.
3.1.2
Write
Writing commands to the Command User Interface enables various modes of operation, including the reading of device data, query, identifier codes, inspection and clearing of the Status Register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 3 on page 16). Standard microprocessor write timings are used.
3.1.3
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output signals D[15:0] are placed in a high-impedance state.
16
Datasheet
28F128J3, 28F640J3, 28F320J3
3.1.4
Standby
CE0, CE1, and CE2 can disable the device (see Table 3 on page 16) and place it in standby mode which substantially reduces device power consumption. D[15:0] outputs are placed in a highimpedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
3.1.5
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0x80. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.2
Device Commands
When the VPEN voltage VPENLK, only read operations from the Status Register, query, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4, "Intel StrataFlash(R) Memory Command Set Definitions" on page 17 defines these commands.
Table 4.
Command
Intel StrataFlash(R) Memory Command Set Definitions (Sheet 1 of 2)
Scalable or Basic Command Set(2) Bus Cycles Req'd. First Bus Cycle Second Bus Cycle Notes
Oper(3) Read Array Read Identifier Codes Read Query SCS/BCS SCS/BCS SCS 1 2 2 Write Write Write
Addr(4) X X X
Data(5,6) 0xFF 0X90 0x98
Oper(3)
Addr(4)
Data(5,6) 1
Read Read
IA QA
ID QD
1,7 1
Datasheet
17
28F128J3, 28F640J3, 28F320J3
Table 4.
Command
Intel StrataFlash(R) Memory Command Set Definitions (Sheet 2 of 2)
Scalable or Basic Command Set(2) Bus Cycles Req'd. First Bus Cycle Second Bus Cycle Notes
Oper(3) Read Status Register Clear Status Register Write to Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Set Block Lock-Bit Clear Block Lock-Bits Protection Program SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS SCS SCS 2 1 >2 2 2 1 1 2 2 2 2 Write Write Write Write Write Write Write Write Write Write Write
Addr(4) X X BA X BA X X X X X X
Data(5,6) 0x70 0x50 0xE8 0x40 or 0x10 0x20 0xB0 0xD0 0xB8 0x60 0x60 0xC0
Oper(3) Read
Addr(4) X
Data(5,6) SRD 1,8 1
Write Write Write
BA PA BA
N PD 0xD0
1,9, 10, 11 1,12,13 1,11,12 1,12,14 1,12
Write Write Write Write
X BA X PA
CC 0x01 0xD0 PD
1 1 1,15 1
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set. 3. Bus operations are defined in Table 2. 4. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Table 5. QA = Query database Address. PA = Address of memory location to be programmed. RCD = Data to be written to the read configuration register. This data is presented to the device on A[16:1]; all other address inputs are ignored. 5. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from Status Register. See Table 6 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 6. The upper byte of the data bus (D[15:8]) during command writes is a "Don't Care" in x16 operation. 7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See Section 4.2 for read identifier code data. 8. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state. 9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0F. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (0xD0) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. See Figure 12, "Write to Buffer Flowchart" on page 52 for additional information 11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued. 12.Attempts to issue a block erase or program to a locked block. 13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup. 14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated. 15.The clear block lock-bits operation simultaneously clears all block lock-bits.
18
Datasheet
28F128J3, 28F640J3, 28F320J3
4.0
Read Operations
The device supports four types of read modes: read array, read identifier, read status or read query. Upon power-up or return from reset, the device defaults to read array mode. To change the device's read mode, the appropriate Read command must be written to the device. (See Section 3.2, "Device Commands" on page 17.) See Section 8.0, "Special Modes" on page 30 for details regarding read status, read ID, and CFI query modes. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 3, "Chip Enable Truth Table" on page 16), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 3), select the memory device. OE# is the data output (D[15:0]) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at VIH.
4.1
Read Array
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. The read configuration register defaults to asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. If the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPEN voltage.
4.1.1
Asynchronous Page-Mode Read
Asynchronous Page Mode is the default read mode on power-up or reset. To perform a page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous page mode reads are permitted in all blocks and is used to access register information, but only one word is loaded into the page buffer during register access. In asynchronous page mode, array data is sensed and loaded into a page buffer. After the initial delay, the first word out of the page buffer corresponds to the initial address. Address bits A[2:0] determine which word is output from the page buffer. Subsequent reads from the device come from the page buffer, and are output on D[15:0] after a minimum delay as long as address bits A[2:0] are the only address bits that change. Data can be read from the page buffer multiple times, and in any order. If address bits A[MAX:3] change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer.
4.2
Read Identifier Codes
The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See Figure 3.2 on page 17 for details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read mode. To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier
Datasheet
19
28F128J3, 28F640J3, 28F320J3
Codes command functions independently of the VPEN voltage. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read Table 5. Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit Block Lock Configuration * Block Is Unlocked * Block Is Locked * Reserved for Future Use Address(1) 00000 00001 00001 00001
X0002
(2)
Data (00) 89 (00) 16 (00) 17 (00) 18
D0 = 0 D0 = 1 D[7:1]
NOTES: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block's lock configuration code.
4.3
Read Status Register
The Status Register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the Status Register until another valid command is written. Pagemode reads are not supported in this read mode. The Status Register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 3, "Chip Enable Truth Table" on page 16). OE# must toggle to VIH or the device must be disabled before further reads to update the Status Register latch. The Read Status Register command functions independently of the VPEN voltage. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR7 is valid until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check SR7), all contents of the Status Register are valid when read.
20
Datasheet
28F128J3, 28F640J3, 28F320J3
Table 6.
WSMS bit 7 High Z When Busy? No Yes
Status Register Definitions
ESS bit 6 ECLBS bit 5 PSLBS bit 4 VPENS bit 3 PSS bit2 DPS bit 1 R bit 0
Status Register Bits SR7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR5 = ERASE AND CLEAR LOCK-BITSSTATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in Setting Lock-Bit 0 = Successful Set Block Lock Bit SR3 = PROGRAMMING VOLTAGE STATUS 1 = Low Programming Voltage Detected, Operation Aborted 0 = Programming Voltage OK SR2 = PROGRAM SUSPEND STATUS 1 = Program suspended 0 = Program in progress/completed SR1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit Detected, Operation Abort 0 = Unlock
Notes Check STS or SR7 to determine block erase, program, or lock-bit configuration completion. SR[6:0] are not driven while SR7 = "0."
Yes Yes Yes
If both SR5 and SR4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
Yes
SR3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences.
Yes
SR1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read Identifier Codes command to determine block lock-bit status. SR0 is reserved for future use and should be masked when polling the Status Register.
Yes
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 7.
WBS bit 7 High Z When Busy? No Yes
eXtended Status Register Definitions
Reserved bits 6--0
Status Register Bits
Notes After a Buffer-Write command, XSR7 = 1 indicates that a Write Buffer is available. SR[6:0] are reserved for future use and should be masked when polling the Status Register.
XSR7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available XSR6-XSR0 = RESERVED FOR FUTURE ENHANCEMENTS
Datasheet
21
28F128J3, 28F640J3, 28F320J3
4.4
Read Query/CFI
The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any information from the query register, execute the Read Query Register command. See Section 3.2, "Device Commands" on page 17 for details on issuing the CFI Query command. Refer to Appendix B, "Query Structure Overview" on page 46 for a detailed explanation of the CFI register. Information contained in this register can only be accessed by executing a single-word read.
5.0
Programming Operations
The device supports two different programming methods: word programming, and write-buffer programming. Successful programming requires the addressed block to be unlocked. An attempt to program a locked block will result in the operation aborting, and SR1 and SR4 being set, indicating a programming error. The following sections describe device programming in detail.
5.1
Byte/Word Program
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs SRD when read (see Figure 14, "Byte/Word Program Flowchart" on page 54). The CPU can detect the completion of the program event by analyzing the STS signal or SR7. When program is complete, SR4 should be checked. If a program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in Read Status Register mode until it receives another command. Reliable byte/word programming can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN VPENLK, SR4 and SR3 will be set. Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/word program is attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set.
5.2
Write to Buffer
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure 12, "Write to Buffer Flowchart" on page 52). At this point, the eXtended Status Register (XSR, see Table 7) information is loaded and XSR7 reverts to "buffer available" status. If XSR7 = 0, the write buffer is not available. To retry, continue monitoring XSR7 by issuing the Write to Buffer setup command with the Block Address until XSR7 = 1. When XSR7 transitions to a "1," the buffer is ready for loading.
22
Datasheet
28F128J3, 28F640J3, 28F320J3
Next, a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated and SR5 and SR4 will be set. For additional buffer writes, issue another Write to Buffer Setup command and check XSR7. If an error occurs while writing, the device will stop writing, and SR4 will be set to indicate a program failure. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. If a program error is detected, the Status Register should be cleared. Any time SR4 and/or SR5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an "Invalid Command/Sequence" error and SR5 and SR4 will be set. Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted while VPEN VPENLK, SR4 and SR3 will be set. Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding block lock-bit be reset. If a buffered write is attempted when the corresponding block lock-bit is set, SR1 and SR4 will be set.
5.3
Program Suspend
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output SRD when read after the Program Suspend command is written. Polling SR7 can determine when the programming operation has been suspended. When SR7 = 1, SR2 should also be set, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. SR2 and SR7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program Resume command is written, the device automatically outputs SRD when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 15, "Program Suspend/Resume Flowchart" on page 55.
Datasheet
23
28F128J3, 28F640J3, 28F320J3
5.4
Program Resume
To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 15, "Program Suspend/Resume Flowchart" on page 55).
6.0
Erase Operations
Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level one. To determine the status of a block erase, poll the Status Register and analyze the bits. This following section describes block erase operations in detail.
6.1
Block Erase
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs SRD when read (see Figure 16, "Block Erase Flowchart" on page 56). The CPU can detect block erase completion by analyzing the output of the STS signal or SR7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register. When the block erase is complete, SR5 should be checked. If a block erase error is detected, the Status Register should be cleared before system software attempts corrective actions. The CUI remains in Read Status Register mode until a new command is issued. This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both SR4 and SR5 being set. Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. If block erase is attempted while VPEN VPENLK, SR3 and SR5 will be set. Successful block erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the corresponding block lock-bit is set, SR1 and SR5 will be set.
6.2
Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs SRD when read after the Block Erase Suspend command is written. Polling SR7 then SR6 can determine when the block erase operation has been suspended (both will be set). In default mode, STS will also transition to VOH. Specification tWHRH defines the block erase suspend latency.
24
Datasheet
28F128J3, 28F640J3, 28F320J3
At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, SR7 will return to "0" and STS output (in default mode) will transition to VOL. However, SR6 will remain "1" to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. SR6 and SR7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs SRD when read (see Figure 17, "Block Erase Suspend/Resume Flowchart" on page 57). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
6.3
Erase Resume
To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume the program operations first. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 16, "Block Erase Flowchart" on page 56.
Datasheet
25
28F128J3, 28F640J3, 28F320J3
7.0
Security Modes
This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail.
7.1
Set Block Lock-Bit
A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read (see Figure 18 on page 58). The CPU can detect the completion of the set lock-bit event by analyzing the STS signal output or SR7. When the set lock-bit operation is complete, SR4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in SR4 and SR5 being set. Also, reliable operations occur only when VCC and VPEN are valid. With VPEN VPENLK, lock-bit contents are protected against alteration.
7.2
Clear Block Lock-Bits
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lockbits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs Status Register data when read (see Figure 19 on page 59). The CPU can detect completion of the clear block lock-bits event by analyzing the STS signal output or SR7. When the operation is complete, SR5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until another command is issued. This two-step sequence of setup followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR4 and SR5 being set. Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN VPENLK, SR3 and SR5 will be set.
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Datasheet
28F128J3, 28F640J3, 28F320J3
If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.
7.3
Protection Register Program
The 3 Volt Intel StrataFlash(R) memory includes a 128-bit Protection Register that can be used to increase the security of a system design. For example, the number contained in the PR can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming.
7.3.1
Reading the Protection Register
The Protection Register is read in the identification read mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 8 or Table 9 retrieve the specified information. To return to read array mode, write the Read Array command (0xFF).
7.3.2
Programming the Protection Register
Protection Register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Table 8 or Table 9. See Figure 20, "Protection Register Programming Flowchart" on page 60 Any attempt to address Protection Program commands outside the defined PR address space will result in a Status Register error (SR4 will be set). Attempting to program a locked PR segment will result in a Status Register error (SR4 and SR1 will be set).
7.3.3
Locking the Protection Register
The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "0xFFFD" to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a Status Register error (SR4 and SR1 will be set). PR lockout state is not reversible.
Datasheet
27
28F128J3, 28F640J3, 28F320J3
Figure 6. Protection Register Memory Map
A[23:1]: 128 Mbit Word Address
0x88 64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A[22:1]: 64 Mbit A[21:1]: 32 Mbit
128-Bit Protection Register 0 64-bit Segment (Factory-Programmed)
NOTE: A0 is not used in x16 mode when accessing the protection register map (See Table 8 for x16 addressing). For x8 mode A0 is used (See Table 9 for x8 addressing).
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Datasheet
28F128J3, 28F640J3, 28F320J3
Table 8.
Word-Wide Protection Register Addressing
Word Use A8 A7 A6 A5 A4 A3 A2 A1
LOCK 0 1 2 3 4 5 6 7
Both Factory Factory Factory Factory User User User User
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
Table 9.
Byte-Wide Protection Register Addressing
Byte Use A8 A7 A6 A5 A4 A3 A2 A1 A0
LOCK LOCK 0 1 2 3 4 5 6 7 8 9 A B C D E F
Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0.
Datasheet
29
28F128J3, 28F640J3, 28F320J3
7.4
Array Protection
The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program operation, poll the Status Register and analyze the bits.
8.0
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to configure the STS signal.
8.1
Set Read Configuration
This command is not supported on this product. This device will default to the asynchronous page mode. If this command is given to the device, it will not affect the operation of the device.
8.1.1
Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No configuration is required. Status Register and identifier only support standard word/byte single read operations.
Table 10. Read Configuration Register Definition
RM 16 (A16) R 8 R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3
Notes
R 10 R 2
R 9 R 1
RCR.16 = READ MODE (RM) 0 = Standard Word/Byte Reads Enabled (Default) 1 = Page-Mode Reads Enabled RCR.15-1 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Read mode configuration effects reads from the flash array. Status Register, query, and identifier reads support standard word/byte read cycles. These bits are reserved for future use. Set these bits to "0."
8.2
STS
The Status (STS) signal can be configured to different states using the Configuration command. Once the STS signal has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/ BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 11, "STS Configuration Coding Definitions" on page 31 displays the possible STS configurations.
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Datasheet
28F128J3, 28F640J3, 28F320J3
To reconfigure the Status (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with the Configuration command resets the STS signal to the default RY/BY# level mode. The possible configurations and their usage are described in Table 11, "STS Configuration Coding Definitions" on page 31. The Configuration command may only be given when the device is not busy or suspended. Check SR7 for device status. An invalid configuration code will result in both SR4 and SR5 being set. When configured in one of the pulse modes, the STS signal pulses low with a typical pulse width of 250 ns. Table 11. STS Configuration Coding Definitions
D7 D6 D5 D4 D3 D2 D1 Pulse on Program Complete (1) Notes
Used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. Used to generate a system interrupt pulse when any flash device in an array has completed a block erase. Helpful for reformatting blocks after file system free space reclamation or "cleanup." Used to generate a system interrupt pulse when any flash device in an array has completed a program operation. Provides highest performance for servicing continuous buffer write operations. Used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired.
D0 Pulse on Erase Complete (1)
Reserved
D[1:0] = STS Configuration Codes
00 = default, level mode; device ready indication 01 = pulse on Erase Complete
10 = pulse on Program Complete 11 = pulse on Erase or Program Complete
NOTES: 1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns. 2. An invalid configuration code will result in both SR4 and SR5 being set.
Datasheet
31
28F128J3, 28F640J3, 28F320J3
9.0
Power and Reset
This section provides an overview of some system level considerations in regards to the flash device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations.
9.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down VCC and VCCQ together. It is also recommended to power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly before VCC.
9.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 F ceramic capacitor is required across each VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 F electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 F capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance.
9.3
Reset Characteristics
By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 9, "AC Waveform for Reset Operation" on page 42 for detailed information regarding reset timings.
32
Datasheet
28F128J3, 28F640J3, 28F320J3
10.0
10.1
Electrical Specifications
Absolute Maximum Ratings
This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute maximum ratings are shown in Table 12.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 12. Absolute Maximum Ratings
Parameter Maximum Rating
Temperature under Bias Extended Storage Temperature Voltage On Any signal Output Short Circuit Current
-40 C to +85 C -65 C to +125 C -2.0 V to +5.0 V(1) 100 mA(2)
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC and VPEN signals. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output signals, VCC, and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time.
Datasheet
33
28F128J3, 28F640J3, 28F320J3
10.2
Symbol
Operating Conditions
Parameter Min Max Unit Test Condition
Table 13. Temperature and VCC Operating Conditions
TA VCC VCCQ
Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 V) VCCQ Supply Voltage (2.7 V-3.6 V)
-40 2.70 2.70
+85 3.60 3.60
C V V
Ambient Temperature
34
Datasheet
28F128J3, 28F640J3, 28F320J3
10.3
DC Current Characteristics
Table 14. DC Current Characteristics
Symb ol Parameter Typ Max 1 10 Unit A A Test Conditions Notes
ILI ILO
Input and VPEN Load Current Output Leakage Current
VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND VCC= VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND CMOS Inputs, VCC = VCC Max, Device is disabled (see Table 3, "Chip Enable Truth Table" on page 16), RP# = VCCQ 0.2 V TTL Inputs, VCC = VCC Max, Device is disabled (see Table 3), RP# = VIH RP# = GND 0.2 V, IOUT (STS) = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 3) f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 3) f = 33 MHz, IOUT = 0 mA CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC Device is enabled (see Table 3)
1 1
50 ICCS VCC Standby Current 0.71 ICCD VCC Power-Down Current 50
120
A
1,2,3
2 120
mA
A
15 ICCR VCC Page Mode Read Current 24
20
mA
1,3
29
mA
ICCW
VCC Program or Set Lock-Bit Current VCC Block Erase or Clear Block Lock-Bits Current VCC Program Suspend or Block Erase Suspend Current
35 40 35 40
60 70 70 80 10
mA mA mA mA mA
1,4
ICCE ICCWS ICCES
1,4 1,5
NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 4. Sampled, not 100% tested. 5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR and ICCWS.
Datasheet
35
28F128J3, 28F640J3, 28F320J3
10.4
DC Voltage Characteristics
Table 15. DC Voltage Characteristics
Symbol Parameter Typ Max Unit Test Conditions Notes
VIL VIH
Input Low Voltage Input High Voltage
-0.5 2.0
0.8 VCCQ + 0.5 0.4
V V V V V V VCCQ = VCCQ Min IOL = 2 mA VCCQ = VCCQ Min IOL = 100 A VCCQ = VCCQ Min IOH = -2.5 mA VCCQ = VCCQ Min IOH = -100 A
2 2
VOL
Output Low Voltage 0.2 0.85 x VCCQ VCCQ - 0.2 VPEN Lockout during Program, Erase and Lock-Bit Operations VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage 2.7 2.2 2.2 3.6
1,2
VOH
Output High Voltage
1,2
VPENLK VPENH VLKO
V V V
2,3,4 3,4 5
NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 4. Typically, VPEN is connected to VCC (2.7 V-3.6 V). 5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max).
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Datasheet
28F128J3, 28F640J3, 28F320J3
11.0
11.1
AC Characteristics
Read Operations
Table 16. Read Operations (Sheet 1 of 2)
Versions (All units in ns unless otherwise noted) # Sym Parameter VCC = 2.7 V-3.6 V (3) VCCQ = 2.7 V-3.6 V (3) Density Min Max Notes
32 Mbit R1 tAVAV Read/Write Cycle Time 64 Mbit 128 Mbit 32 Mbit R2 tAVQV Address to Output Delay 64 Mbit 128 Mbit 32 Mbit R3 tELQV CEX to Output Delay 64 Mbit 128 Mbit R4 tGLQV OE# to Non-Array Output Delay 32 Mbit R5 tPHQV RP# High to Output Delay 64 Mbit 128 Mbit R6 R7 R8 R9 R10 R11 R12 R13 R14 tELQX tGLQX tEHQZ tGHQZ tOH tELFL/tELFH tFLQV/tFHQV tFLQZ tEHEL CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low
110 115/120 120/150 110 115/120 120/150 110 115/120 120/150 50 150 180 210 0 0 35 15 0 10 1000 1000 0
1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,4 1,2 1,2 1,2 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2,5 1,2 1,2,5 1,2,5
Datasheet
37
28F128J3, 28F640J3, 28F320J3
Table 16. Read Operations (Sheet 2 of 2)
Versions (All units in ns unless otherwise noted) # Sym Parameter VCC = 2.7 V-3.6 V (3) VCCQ = 2.7 V-3.6 V (3) Density Min Max Notes
R15 R16
tAPA tGLQV
Page Address Access Time OE# to Array Output Delay
25 25
5, 6 4
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 3) without impact on tELQV. 3. See Figure 10, "Transient Input/Output Reference Waveform for VCCQ = 2.7 V-3.6 V" on page 42 and Figure 11, "Transient Equivalent Testing Load Circuit" on page 43 for testing characteristics. 4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to Status Register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Figure 7. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations
VIH
ADDRESSES [A 23-A3]
VIL VIH Valid Address
R1 Valid Valid Address Address Valid Address R14
ADDRESSES [A 2-A0]
VIL
Disabled (VIH)
CEX [E]
Enabled (VIL) R2 R8 VIH VIL R3 R4 or R16 R5 High Z R6 Valid Output R7 R15 Valid Output Valid Output Valid Output R10 High Z R9
OE# [G]
WE# [W]
VIH VIL
DATA [D/Q] VOH DQ0-DQ15
VOL VIH VIL VIH
VCC
RP# [P]
VIL VIH
R11
R12 R13
BYTE# [F]
VIL
0606_16
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3). For standard word/byte read operations, R15 (tAPA) will equal R2 (tAVQV). When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to Status Register reads, query reads, or device identifier reads.
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Datasheet
28F128J3, 28F640J3, 28F320J3
11.2
Write Operations
Table 17. Write Operations
Versions # Symbol Parameter Valid for All Speeds Min Max Unit Notes
W1 W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15
tPHWL (tPHEL) tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL
RP# High Recovery to WE# (CEX) Going Low CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High
1 0 70 50 55 0 0 0 30 0 35 500 0
s ns ns ns ns ns ns ns ns ns ns ns ns
1,2,3 1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 1,2,8 1,2,3,8,9
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[1,3,4:5] = 0).
Datasheet
39
28F128J3, 28F640J3, 28F320J3
11.3
Block Erase, Program, and Lock-Bit Configuration Performance
Table 18. Configuration Performance
# Sym Parameter Typ Max(8) Unit Notes
W16 W16 tWHQV3 tEHQV3
Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command)
218 210 0.8 1.0 64 0.5 25 26
654 630 2.4 5.0 75/85 0.70/1.4 75/90 35/40
s s sec sec s sec s s
1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,10 1,2,3,9 1,2,3,9
W16 W16 W16 W16 W16
tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH
Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read
NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 s/byte (typical). 7. Effective per-word program time (tWHQV2, tEHQV2) is 13.6 s/word (typical). 8. Max values are measured at worst case temperature and VCC corner after 100k cycles (except as noted). 9. Max values are expressed at -25 C/-40 C. 10.Max values are expressed at 25 C/-40 C.
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Datasheet
28F128J3, 28F640J3, 28F320J3
Figure 8. AC Waveform for Write Operations
A VIH VIL Disabled (VIH) CEX, (WE#) [E(W)] Enabled (VIL) VIH OE# [G] VIL
W2 W1
B
C
D
E
F
ADDRESSES [A]
AIN W5
AIN W8
W6
W12
W9
W16
Disabled (VIH) WE#, (CEX) [W(E)] Enabled (VIL)
W4
W3 W7 DIN DIN W13 Valid SRD DIN High Z
VIH DATA [D/Q] VIL VOH STS [R] VOL VIH VIL
RP# [P]
W11
W15
VPENH VPENLK VPEN [V] VIL
0606_17
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 3). STS is shown in its default mode (RY/BY#).
a. b. c. d. e. f.
VCC power-up and standby. Write block erase, write buffer, or program setup. Write block erase or write buffer confirm, or valid address and data. Automated erase delay. Read Status Register or query data. Write Read Array command.
Datasheet
41
28F128J3, 28F640J3, 28F320J3
11.4
Reset Operation
Figure 9. AC Waveform for Reset Operation
STS (R)
VIH VIL
P2
RP# (P)
VIH VIL
P1
0606_18
NOTE: STS is shown in its default mode (RY/BY#).
Table 19. Reset Specifications
# Sym Parameter Min Max Unit Notes
P1
tPLPH tPHRH
RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration
35
s
1,2
P2
100
ns
1,3
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
11.5
AC Test Conditions
Figure 10. Transient Input/Output Reference Waveform for VCCQ = 2.7 V-3.6 V
VCCQ Input 0.0 V CCQ/2 Test Points VCCQ/2 Output
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
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Datasheet
28F128J3, 28F640J3, 28F320J3
Figure 11. Transient Equivalent Testing Load Circuit
1.3V 1N914 RL = 3.3 k Device Under Test Out CL
NOTE: CL Includes Jig Capacitance Test Configuration CL (pF)
VCCQ = VCC = 2.7 V-3.6 V
30
11.6
Capacitance
TA = +25 C, f = 1 MHz
Symbol Parameter(1) Type Max Unit Condition
CIN COUT
Input Capacitance Output Capacitance
6 8
8 12
pF pF
VIN = 0.0 V VOUT = 0.0 V
NOTES: 1. Sampled, not 100% tested.
Datasheet
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28F128J3, 28F640J3, 28F320J3
Appendix A Write State Machine (WSM)
A.1 TBD
44
Datasheet
28F128J3, 28F640J3, 28F320J3
Appendix B Common Flash Interface
The Common Flash Interface(CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forwardand backward-compatible software support for the specified flash device families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (D[7:0]) and 00h in the high byte (D[15:8]). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
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28F128J3, 28F640J3, 28F320J3
Table 20. Summary of Query Structure Output as a Function of Device and Mode
Device Type/ Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset Hex Code ASCII Value Query data with byte addressing Hex Offset Hex Code ASCII Value
x16 device x16 mode x16 device x8 mode
10h
10: 11: 12:
0051 0052 0059 N/A(1)
"Q" "R" "Y"
N/A(1)
20: 21: 22: 20: 21: 22:
51 00 52 51 51 52
"Q" "Null" "R" "Q" "Q" "R"
NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices.
Table 21. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Offset A15-A0 Hex Code D15-D0 Value Offset A7-A0 Byte Addressing Hex Code D7-D0 Value
0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ...
0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ...
"Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ...
20h 21h 22h 23h 24h 25h 26h 27h 28h ...
51 51 52 52 59 59 P_IDLO P_IDLO P_IDHI ...
"Q" "Q" "R" "R" "Y" "Y" PrVendor ID # ID # ...
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail.
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Table 22. Query Structure
Offset Sub-Section Name Description Notes
00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h
P(3)
Manufacturer Code Device Code Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Block-Specific Information
Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information
1 1 1,2 1 1 1 1 1,3
Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.
B.3
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations.
Table 23. Block Status Register
Offset Length Description Address Value
(BA+2)h
(1)
1
BA+2: (bit 1-7): 0 NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location in word mode).
Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR 1-7: Reserved for Future Use
BA+2: BA+2:
--00 or --01 (bit 0): 0 or 1
B.4
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 24. CFI Identification (Sheet 1 of 2)
Offset Length Description Add. Hex Code Value
10h 13h 15h 17h
3 2 2 2
Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code.
10 11: 12: 13: 14: 15: 16: 17:
--51 --52 --59 --01 --00 --31 --00 --00
"Q" "R" "Y"
Datasheet
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28F128J3, 28F640J3, 28F320J3
Table 24. CFI Identification (Sheet 2 of 2)
Offset Length Description Add. Hex Code Value
19h
2
0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
18: 19: 1A:
--00 --00 --00
B.5
System Interface Information
The following device information can optimize system interface software.
Table 25. System Interface Information
Offset Length Description Add. Hex Code Value
1Bh
1
1Ch
1
1Dh
1
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1 1
VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical
1B:
--27
2.7 V
1C:
--36
3.6 V
1D:
--00
0.0 V
1E: 1F: 20: 21: 22: 23: 24: 25: 26:
--00 --07 --07 --0A --00 --04 --04 --04 --00
0.0 V 128 s 128 s 1s NA 2 ms 2 ms 16 s NA
B.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 26. Device Geometry Definition (Sheet 1 of 2)
Offset Length Description Code See Table Below
27h 28h 2Ah
1 2 2
"n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 "n" such that maximum number of bytes in write buffer = 2n
27: 28: 29: 2A: 2B: --02 --00 --05 --00 x8/ x16 32
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Datasheet
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Table 26. Device Geometry Definition (Sheet 2 of 2)
Offset Length Description Code See Table Below
2Ch
1
2Dh
4
Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes
2C:
--01
1
2D: 2E: 2F: 30:
Device Geometry Definition
Address 32 Mbit 64 Mbit 128 Mbit
27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30:
--16 --02 --00 --05 --00 --01 --1F --00 --00 --02
--17 --02 --00 --05 --00 --01 --3F --00 --00 --02
--18 --02 --00 --05 --00 --01 --7F --00 --00 --02
B.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information.
Table 27. Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value
(P+0)h (P+1)h (P+2)h (P+3)h (P+4)h
3
Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII
1 1
31: 32: 33: 34: 35:
--50 --52 --49 --31 --31
"P" "R" "I" "1" "1"
Datasheet
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28F128J3, 28F640J3, 28F320J3
Table 27. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value
(P+5)h (P+6)h (P+7)h (P+8)h
4
(P+9)h
1
(P+A)h (P+B)h
2
(P+C)h
1
(P+D)h
1
Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant Individual block locking supported bit 6 Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts
36: --0A 37: --00 38: --00 39: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 1(1) bit 4 = 0 bit 5 = 0 bit 6 = 1 bit 7 = 1 bit 8 = 0 3A: --01
No Yes Yes Yes(1) No No Yes Yes No
bit 0 = 1 3B: --01 3C: --00 bit 0 = 1 bit 1 = 0 3D: --33
Yes
Yes No 3.3 V
3E:
--00
0.0 V
NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0."
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Datasheet
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Table 28. Protection Register Information
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value
(P+E)h
1
(P+F)h (P+10)h (P+11)h (P+12)h
4
Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are userprogrammable. Bits 0-15 point to the protection register lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user-programmable bytes
3F:
--01
01
40:
--00
00h
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Table 29. Burst Read Information
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Add. Hex Code Value
Page Mode Read capability (P+13)h 1 bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Reserved for future use 44: --03 8 byte
(P+14)h
1
45: 46:
--00
0
(P+15)h NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Datasheet
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28F128J3, 28F640J3, 28F320J3
Appendix C Flow Charts
Figure 12. Write to Buffer Flowchart
Start
Command Cycle - Issue Write-to-Buf f er Command - Address = Any address in block - Data = 0xE8
Check Ready Status - Read Status Register Command not required - Perf orm read operation - Read Ready Status on signal D7
No
No
D7 = 1?
Yes
Write to Buf f er Time-Out?
Yes
Write Word Count - Address = Any address in block - Data =word count - Valid range = 0x0 thru 0x1F
Write Buffer Data - Fill write buf f er up to word count - Address = Address(es) within buf f er range - Data = Data to be written
Confirm Cycle - Issue Conf irm Command - Address = Any address in block - Data = 0xD0
Read Status Register See Status Register Flowchart
Yes
Any Errors?
No
Error-Handler User-def ined routine
End
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Figure 13. Status Register Flowchart
Start
Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70
Data Cycle - Read Status Register SR[7:0]
SR7 = '1'
No
Y es
- Set/Reset by WSM
SR6 = '1'
Y es
Erase Suspend See Suspend/Resume Flowchart
No
SR2 = '1'
Y es
Program Suspend See Suspend/Resume Flowchart
No
SR5 = '1'
Y es
SR4 = '1'
Y es
Error Command Sequence
No
No Error Erase Failure
Y es SR4 = '1'
Error Program Failure
- Set by WSM - Reset by user - See Clear Status Register Command
No
SR3 = '1'
Y es
Error V PEN < VPENLK
No
SR1 = '1'
Y es
Error Block Locked
No
End
0606_07A
Datasheet
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28F128J3, 28F640J3, 28F320J3
Figure 14. Byte/Word Program Flowchart
Start
Bus Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data = 40H Addr = Location to Be Programmed Data = Data to Be Programmed Addr = Location to Be Programmed Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address Write Data and Address Read Status Register 0
Read (Note 1) Standby
SR.7 = 1 Full Status Check if Desired Byte/Word Program Complete
1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming to Voltage Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH , Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Check SR.4 1 = Programming Error
1 Device Protect Error
Standby
Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
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Figure 15. Program Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Program Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Programming Suspended 0 = Programming Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.2 = Programming Completed Write 1 Write FFH Read
Read Array
Data = FFH Addr = X Read array locations other than that being programmed.
Program Resume
Data = D0H Addr = X
Read Data Array
No Done Reading Yes Write D0H Write FFH
Programming Resumed
Read Array Data
0606_08
Datasheet
55
28F128J3, 28F640J3, 28F320J3
Figure 16. Block Erase Flowchart
Bus Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note 1)
Start
Command Erase Block Erase Confirm
Comments Data = 20H Addr = Block Address Data = D0H Addr = X Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy
Read
Standby Write Confirm D0H Block Address
1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Suspend Erase Loop
Read Status Register No
SR.7 =
0
Suspend Erase
Yes
1 Full Status Check if Desired
Erase Flash Block(s) Complete
0606_09
56
Datasheet
28F128J3, 28F640J3, 28F320J3
Figure 17. Block Erase Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Erase Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.6 = Block Erase Completed
Erase Resume
Data = D0H Addr = X
1 Read Read or Program? Read Array Data Done? Yes Write D0H Write FFH Program Loop Program
No
Block Erase Resumed
Read Array Data
0606_10
Datasheet
57
28F128J3, 28F640J3, 28F320J3
Figure 18. Set Block Lock-Bit Flowchart
Start
Bus Operation Write
Command Set Block Lock-Bit Setup Set Block Lock-Bit Confirm
Comments Data = 60H Addr =Block Address Data = 01H Addr = Block Address Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H, Block Address Write 01H, Block Address
Write
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired
0
Repeat for subsequent lock-bit operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful
0606_11b
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
Voltage Range Error
Standby
Command Sequence Error
Standby
Set Lock-Bit Error
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
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Figure 19. Clear Lock-Bit Flowchart
Start
Bus Operation Write
Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm
Comments Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H
Write
Write D0H
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired Clear Block Lock-Bits Complete
0
Write FFH after the clear lock-bits operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful
0606_12b
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
Voltage Range Error
Standby
Command Sequence Error
Standby
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command.
Clear Block Lock-Bits Error
If an error is detected, clear the status register before attempting retry or other error recovery.
Datasheet
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28F128J3, 28F640J3, 28F320J3
Figure 20. Protection Register Programming Flowchart
Start
Bus Operation Write Write
Command Protection Program Setup Protection Program
Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 = 1? Yes Full Status Check if Desired
No
Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPEN Range Error 0,1 SR.1, SR.4 =
Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 VPEN Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted
1
0
1
Protection Register Programming Error Attempted Program to Locked Register Aborted
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
1,1 SR.1, SR.4 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Program Successful
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Appendix D Mechanical Information
Figure 21. 56-Lead TSOP Package Drawing and Specifications
Z
See Notes 1 and 3
Pin 1
See Note 2
A2 e
E
See Detail B
Y
D1 D
A1 Seating Plane
See Detail A
A
Detail A Detail B
C
0
b
[231369-90]
L
A5569-01
Table 30. 56-Lead TSOP Dimension Table
Millimeters Sym Min Nom Max Notes Min Inches Nom Max Notes
Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset
A A1 A2 b c D1 E e D L N 19.800 0.500 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 20.00 0.600 56 0 3
1.200 0.002 1.025 0.200 0.200 18.600 14.200 4 4 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 20.200 0.700 0.780 0.020 0.787 0.024 56 5 0.100 0.150 0.250 0.350 0.006 0.010 0 3
0.047
0.040 0.008 0.008 0.732 0.559 4 4
0.795 0.028
Y Z
5 0.004 0.014
Datasheet
61
28F128J3, 28F640J3, 28F320J3
Figure 22. 3 Volt Intel StrataFlash(R) Memory Easy BGA Mechanical Specifications
Ball A1 Corner Ball A1 Corner
D
S1
1 A B C D E E F G H
2
3
4
5
6
7
8 A B C D E F G
8
7
6
5
4
3
2
1
S2
b
e H
Top View - Ball side down
Bottom View - Ball Side Up
A1 A2 A
Seating Plane
Y
Note: Drawing not to scale
Side View
Dimensions Table
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Dista nc e A long D Corner to Ball A1 Dista nc e A long E Symbol A A1 A2 b D E [e] N Y S1 S2 Millimeters M in Nom 0.250 0.330 9.900 12.900 0.780 0.430 10.000 13.000 1.000 64 1.500 3.000 0.530 10.100 13.100 Max 1.200 Notes Inches Min 0.0098 0.0130 0.3898 0.5079 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0591 0.1181 0.0209 0.3976 0.5157 Nom Ma x 0.0472
1 1
1.400 2.900
0.100 1.600 3.100
1 1
0.0551 0.1142
0.0039 0.0630 0.1220
Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change.
NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm
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Figure 23. 3 Volt Intel StrataFlash(R) Memory VF BGA Mechanical Specifications
Ball A1 Corner D S1 Ball A1 Corner
S2 1 A B C E D E F 2 3 4 5 6 7 8 A B C D E F b e 8 7 6 5 4 3 2 1
Top View - Bump S ide Down
Bottom View - Ball Side Up
A1 A2 A Seating Plane Side View Note: Drawing not to scale
Y
Dimensions Table
Millimeters Inches Min Symbol M in Nom Max Notes Package Height A 1.000 Ball Height A1 0.150 0.0059 0.665 Package Body Thickness A2 Ball (Lead) Width b 0.325 0.375 0.425 0.0128 D 7.186 7.286 7.386 1 0.2829 Package Body Lengt h E 10.750 10.850 10.950 1 0.4232 Pitch [e] 0.750 Ball (Lead) Count N 48 Seating Plane Coplanarity Y 0.100 Corner to Ball A1 Dista nc e Along D S1 0.918 1.018 1.118 1 0.0361 Corner to Ball A1 Dista nc e Along E S2 3.450 3.550 3.650 1 0.1358 Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject t o change. Nom Max 0.0394
0.0262 0.0148 0.2868 0.4272 0.0295 48 0.0401 0.1398
0.0167 0.2908 0.4311
0.0039 0.0440 0.1437
NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm
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Appendix E Design Considerations
E.1 Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 3) while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
E.2
STS and Block Erase, Program, and Lock-Bit Configuration Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. It is recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS signal, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode.
E.3
Input Signal Transitions--Reducing Overshoots and Undershoots When Using Buffers or Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications. (See "Absolute Maximum Ratings" on page 33.) Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or lightdrive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For additional information, please refer to AP-647, 5 Volt Intel StrataFlash(R) Memory Design Guide (Order Number: 292205).
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E.4
VCC, VPEN, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# VIH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the Status Register. The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.
E.5
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed.
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Appendix F Additional Information
Order Number
(R)
Document/Tool 3 Volt Intel StrataFlashTM Memory 28F128J3, 28F640J3, 28F320J3 Specification Update Intel(R) Persistent Storage Manager (IPSM) User's Guide Software Manual Intel(R) Flash Data Integrator (FDI) User's Guide Software Manual 3 Volt Synchronous Intel StrataFlash(R) Memory 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 AP-732 3 Volt Intel StrataFlash(R) Memory J3 to K3/K18 Migration Guide AP-689 Using Intel(R) Persistent Storage Manager 5 Volt Intel(R) StrataFlashTM MemoryI28F320J5 and 28F640J5 datasheet AP-677 Intel(R) StrataFlashTM Memory Technology AP-664 Designing Intel(R) StrataFlashTM Memory into Intel(R) Architecture AP-663 Using the Intel(R) StrataFlashTM Memory Write Buffer AP-660 Migration Guide to 3 Volt Intel(R) StrataFlashTM Memory AP-646 Common Flash Interface (CFI) and Command Sets Intel(R) Flash Memory Chip Scale Package User's Guide
298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 298161
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http:// developer.intel.com/design/flash/isf.
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Appendix G Ordering Information
RC2 8 F 1 2 8 J 3 A - 1 5 0
Package E = 56-Lead TSOP TE = 56-Lead TSOP RC = 64-Ball Easy BGA GE = 48-Ball VF BGA Product line designator for all Intel(R) Flash products Device Density 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Access Speed (ns) 1 128 Mbit = 120 or 150 64 Mbit = 115 or 120 32 Mbit = 110 Process Technology A = 0.25 m C = 0.18 m Voltage (V CC /V PEN ) 3 = 3 V/3 V Product Family J = Intel(R) StrataFlash TM memory, 2 bits-per-cell
NOTE: 1. These speeds are for either the standard asynchronous read access times or for the first access of a pagemode read sequence.
VALID COMBINATIONS
56-Lead TSOP 64-Ball Easy BGA 48-Ball VF BGA
E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150
RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150
GE28F320J3A-110 GE28F320J3C-110 GE28F640J3C-115 GE28F640J3C-120
Datasheet
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